High speed data acquisition technology is receiving increasing attention attributable to exponentially increasing management and measure usage. This technique performs the acquisition of physical signal, conversion of analog signal to digital signal and storing of the information. FPGA, as the core of the data acquisition system, collects and stores the information. The analog to digital converter (ADC) adopted in the system is a high-speed chip, ADC0809 data acquisition component which is a monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. This paper presents an idea behind the hardware designing of ADC and simulation of ADC controller code used for FPGA implementation of high speed data acquisition system. Xilinx Spartan3 does not have a facility of in build ADC so designing of ADC and interfacing it with FPGA is extremely necessary.
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